Mentor Questa Formal 2021.1

KEY FEATURES
Advanced Verilog Simulator
The Questa Advanced Simulator achieves industry-leading performance and capacity through very aggressive, global compile and simulation optimization algorithms for SystemVerilog and VHDL.

INDUSTRY-LEADING

High Performance and Capacity
Questa Advanced Simulation achieves industry-leading performance and capacity through very aggressive, global compile and simulation optimization algorithms of SystemVerilog and VHDL, improving SystemVerilog and mixed VHDL/SystemVerilog RTL simulation performance by up to 10X.



Questa Verification Management provides a shared platform and environment for comprehensive verification management of design process, tools and data within a scalable, modular solution.
MULTI-CORE SIMULATION

High-performance, multi-language engine
The Questa Advanced simulator supports all design languages and constructs, and either automatically or manually partitions the design to run in parallel while maintaining a single database for debug and coverage.


Questa Simulation tools enable design teams to verify the architecture and behavior planned for an implementation.
AUTOMATED STIMULI GENERATION

Testbench Automation
The Questa Advanced Simulator supports the most comprehensive solutions for testbench automation in the industry, enabling automatic creation of complex, input-stimuli using SystemVerilog or SystemC Verification (SCV) library constructs, and combining these forms of stimulus generation with functional coverage to identify the functionality exercised by the automatically-generated stimulus.